1. Field
The present invention relates to semiconductor technology, and more specifically to a clock boosting scheme for Complimentary Metal-Oxide-Semiconductor (CMOS) devices.
2. Background
CMOS semiconductor fabrication technologies have advanced to the point where the transistors are becoming progressively smaller in form factor. For example, sub-micron CMOS processes are becoming mainstream for fabrication of silicon devices on many consumer electronic systems. Smaller transistor sizes provide for, among other advantages, the capability to place more functions on a single die, decreased power requirements, and increased operating frequencies of the integrated circuit device. The increased frequencies are due in part to the smaller gate capacitances associated with the sub-micron transistors as well as a lower supply voltage swing.
Power dissipation limitations of the transistors and other reliability issues generally necessitate the use of lower supply voltages for integrated circuits incorporating sub-micron CMOS processes. For instance, too high a regular supply voltage will result in higher currents and a resulting energy dissipation that will, over time, tax the delicate structures of these ultra-small transistors, and eventually result in a degradation of functionality. Consequently, circuit designers generally rely on low supply voltages (LSV) in performing analog and digital integrated circuit design for circuits using sub-micron MOS processes.
The use of LSV presents a significant benefit for the operation of digital integrated circuits due to, among other advantages, the lower power dissipation associated with using lower voltages, and the preservation of the structural integrity of the transistors. The use of LSV in connection with analog circuits designed in a sub-CMOS process, conversely, gives rise to certain challenges. One such challenge is presented, for exemplary purposes, in the context of switched-capacitor (“SC”) circuits. Often one or more switches will reside on the signal path in front of a stage of sampling capacitors. A strong demand exists for a switch in various analog circuits, such as switched-capacitor circuits, which covers rail-to-rail voltage swings using LSV. Where the supply voltage is too low, the voltage on the signal path may cause the switch(es) to float or otherwise not operate properly. In such a case for certain values of the input voltage on the signal path, the floating switches may prevent the input signal from being sampled.
An example of this problem is represented in FIGS. 1 and 3. FIG. 3 depicts a basic example of a CMOS switch including NMOS transistor 300 and PMOS transistor 302. Capacitor C (304) represents a sampling capacitor at the output of the signal path Vout. An input voltage Vin is applied to the signal path at 301. Switch 306 represents an ideal sampling switch. The ideal switch is intended to demonstrate the performance of the CMOS switch, and subsequent circuits such as gain or integrator stages are ignored for the purpose of this illustration. The use of capacitor 304 and ideal switch 306 are for clarity and simplicity; the signal path may contain any number of switched capacitors or other analog components or circuits.
In many applications it is desirable for the CMOS switch to pass the signal Vin to the sampling capacitor 304 at Vout through the range where Vin goes from VGND to VDD, or vice versa. That is, whatever the value of Vin, the CMOS switch (comprised of transistors 300 and 302) should be configured to allow for conduction of the signal under certain conditions. Where the power supply is very low, however, a range of amplitude of Vin may exist wherein the output of the switch cannot conduct and the signal cannot be sampled. For example, where the supply voltage VDD is less than the sum of the threshold voltages of NMOS transistor 300 and PMOS transistor 302—namely, (|Vth,p|+Vth,n)—sampling of Vout cannot be achieved through the full signal swing of Vin. This situation represents a major shortcoming of CMOS analog integrated circuits using sub-micron fabrication processes, particularly in switched-capacitor and other analog applications.
FIG. 1 is a graphic illustration of the conductances of NMOS, PMOS, and CMOS switches as a function of the input voltage Vin (see FIG. 3). Plot 100 represents a graph of the conductance gds of transistor 300 as a function of input voltage Vin (node 301). Plot 110 depicts a graph of the conductance gds as a function of Vin. Plot 112 represents a collective graph of the resulting CMOS switch (i.e., transistors 300 and 302) as a function of Vin.
As can be seen graphically in FIG. 1 from plots 100 and 110, the magnitude of the power supply voltage VDD as depicted by dashed vertical line 114 in each plot is less than the sum of the threshold voltages of the two transistors Vth,n (plot 100) and Vth,p (plot 110). Consider the conductance of the CMOS switch as signal Vin goes from a value of VGND up to VDD. Assume also, for the purpose of this illustration, that Φnmos=VDD and Φpmos=VGND. When Vin 301 in FIG. 3 is equal to VGND, then the gate-to-source voltage of transistor 300=VDD>Vth,n; hence, transistor 300 is fully on and at its maximum conductance gds as shown in plot 100.
As Vin in plot 100 becomes progressively larger, the gate to source voltage of NMOS transistor 300 approaches the threshold voltage Vth,n, thereby decreasing the drain current through transistor 300 and conductance gds. When Vin reaches a value of Vdd−νth,n, then the gate-to-source voltage of transistor 300 equals the threshold voltage and the conductance gds of transistor 300 reaches zero as transistor 300 turns off. Transistor 300 remains off as Vin increases to VDD, as shown in plot 100 of FIG. 1.
Plot 110 of FIG. 1 shows the concurrent behavior of PMOS transistor 302 in the same circuit and under the same conditions. When Vin=VGND, then transistor 302 is off. As Vin reaches the threshold value Vth,p of PMOS transistor 302, then transistor 302 begins to turn on, a drain current flows through transistor 302, and the conductance gds of transistor 302 begins to increase. The conductance gds of transistor 302 reaches its maximum value when Vin=VDD, because the gate to source voltage of the PMOS transistor 302 is at its maximum.
Plot 112 of FIG. 1 represents the collective behavior of the CMOS switch in FIG. 3. Plot 112 is a superimposition of plots 100 and 110. From the illustration of plot 112, the problems associated with using LSV in analog circuit design become evident. In particular, a region of operation exists (represented by vertical dashed lines 115 and 116) wherein the CMOS switch is off, and the Vin signal cannot be sampled at the output. The region where the circuit is inoperative in this illustration can be quantified as the region between the lower bound Vin=VDD−Vth,n (line 115) and the upper bound Vin=Vth,p (line 116).
It will be appreciated that the principles of the circuit in FIG. 3 and the behavior of the circuit as shown in FIG. 1 is illustrative in nature, as many other circuits can be constructed which recreate essentially the same problem.
Various techniques to turn on and off floating switches and enable rail-to-rail sampling in analog circuits using LSV have been proposed in the literature. One such technique is to boost the gate voltages of the switching transistors to 2×VDD. Another technique is to boost the gate voltages to VDD+Vin. Using the former technique, only one boosting circuit is needed to feed the various analog circuits. A major disadvantage of the former technique, however, is that the resistance of the switch varies widely as a function of the gate-to-source voltage. More specifically, VGS=2VDD−Vin; therefore, the output resistance of the transistor becomes dependant on Vin. Another disadvantage of using the former technique is the reliability issues that will result given that twice the power supply (2×VDD) is applied to the gates of the transistors, likely causing eventual breakdown of the sub-micron transistor structures. In addition, the high gate voltage may cause undesirable currents to flow as a result of forward biasing the substrate of the transistor.
Using the latter technique has consequently been preferred because a substantially constant switch resistance can be obtained. That is, using the latter technique, VGS=(VDD+Vin)−Vin=VDD. One major disadvantage of the latter scheme is that a boosting circuit is required for each floating switch on the analog portion of the integrated circuit chip. Such a technique would require a substantial increase in both total power consumption and the area of the die as numerous boosting circuits would have to be designed onto the chip.
Accordingly, a demand in the art exists for a reliable switching mechanism in LSV analog circuit applications like switched capacitor circuits that has the capability to cover rail-to-rail (e.g., power to ground) voltage swings using low supply voltages, while not causing unacceptable substrate or other leakage, not unduly increasing circuit complexity, and not introducing reliability problems.